1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for semiconductor devices.
2. Description of the Prior Art
The creation of semiconductor devices, also referred to as Integrated Circuits (IC) has been made possible by the rapid development of supporting technologies such as photolithography and methods of etching. Most of these technologies have over the years had to address concerns created by a continued decrease in device dimensions and increase in device densities. This effort of creating improved performance devices does is not limited in its impact on the device itself but extends into the methods and packages that are used to further interconnect semiconductor devices and to protect these devices from environmental damage. This latter issue has created a packaging technology that is also driven by continuing demands of device miniaturization and denser packaging of devices, this at no penalty to device performance and in a cost-effective manner.
Semiconductor device packaging typically mounts a device on a substrate, such as semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support. Such a substrate can be a relative complex structure, having multiple payers of interconnect metal distributed throughout the height of the substrate in addition to having interconnect traces created on one or both surfaces of the substrate. In addition, in order to enable the mounting of semiconductor over the surface of the substrate, contact pads such as bond pads are typically provided over at least one of the surfaces of a substrate. For more complex packages, several levels of packaging may be applied whereby a semiconductor device is mounted on a substrate and connected to interconnect metal that is part of the substrate, the first level substrate may be further mounted over the surface of a larger substrate from which the device is interconnected to surrounding circuitry or electrical components. Limitations that are imposed on this method of packaging are typically limitations of electrical performance that is imposed on the device by the packaging interface. For instance, of key concerns are RC delays in the transmission of signals over the various interconnect traces. This places a restraint of size and therefore packaging density on the package. Also of concern are considerations of parasitic capacitance and inductance that are introduced by the package since these parameters have a negative impact on device performance, a more serious impact on high frequency device performance. These parasitic components must therefore be minimized or suppressed to the maximum extent possible.
One or the more conventional methods of connecting a semiconductor device to surrounding points of interconnect is the use of a solder bump. Typically a semiconductor device will be provided on the active surface of the device with points of electrical interconnect which electrically access the device. To connect these points of interconnect to for instance a printer circuit board, solder bumps are provided on the surface of the circuit board that align with the points of electrical contact of the device. The creation of this interface is also subject to requirements imposed by electrical performance of the completed package, by requirements of package miniaturization, reliability, cost performance and the like. The invention provides a package that addresses these packaging concerns in addition to others.
U.S. Pat. No. 6,181,569 (Charkravorty) shows a solder bump process and structure that includes trace formation and bump plating.
U.S. Pat. No. 6,107,180 (Munroe et al.) shows a bump process using UBM and solder bumps.
U.S. Pat. No. 5,879,964 (Paik et al.) shows a related bump and interconnect process.